1. Field of the Invention
The present invention relates to a method of accessing memory locations on a network device and more particularly for reading and writing information from a CPU to a memory location on the network device.
2. Description of the Related Art
A switching system may include one or more network devices, such as a Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs. Some devices also include a CPU processing module through which the device interfaces with external CPU ports.
As packets enter the device from multiple ports, they are forwarded to the ingress module where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to the MMU. After performing resource checks on the packets, the MMU transmits the packets to the egress module for further processing and modification. Thereafter, the egress module transmits the packets to at least one destination port, including a CPU port. If the packets are being transmitted to the CPU port, the egress module forwards them through a CPU processing module which transmits the packet to the CPU via the PCI bus.
Each of the ingress module, the MMU, and the egress module includes one or more internal Random Access Memory (RAM) and Content Addressable Memory (CAM) for storing information. For example, the ingress and egress modules may store lookup tables with switching information in the internal RAM/CAM. When the device is initialized, information is stored in each RAM and/or CAM. During normal processing, the information in one or more RAM/CAM may be updated either by the device or by the CPU. To synchronize the information stored in the RAM/CAM with the information stored on the CPU, the CPU may need to access and/or update the information stored in one or more RAM and/or CAM. Previous designs enabled the CPU to obtain all of the information from a RAM/CAM in a bulk transfer operation, i.e., read all of the information at one time. However, these designs provided no bulk transfer write operations from the CPU to the device. Moreover, the bulk read transfer operation was only available on some tables.
As such, if the CPU had to insert and/or delete an entry in a RAM and/or CAM, a table DMA engine in the CPU processing module copied all entries from the table to the CPU. Upon modifying the table, the CPU transmitted one entry at a time to the RAM/CAM to be modified. For a RAM/CAM with a large amount of entries, this operation is not only slow, it is costly since numerous write operations are required in order to update one entry in the RAM/CAM.